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SUSHI'25, Hosted by NIST

Rolling Next-Generation Secure Hardware into Standards

-An Interactive Workshop-

October 22-23, 2025
NIST, 100 Bureau Drive, Gaithersburg, Maryland 20899

TBA soon

The pursuit of digital sovereignty, intensified by global semiconductor shortages and geopolitical tensions, has triggered a wave of initiatives worldwide to strengthen semiconductor technologies and manufacturing at both national and regional levels. As a result, the importance of hardware security and trust in computing systems and supply chains has become more critical than ever.


Hardware security underpins the reliability and integrity of modern computing infrastructures. When compromised, it threatens essential system operations and exposes society to significant risks.


In recent years, however, vulnerabilities in hardware design and implementation have increasingly emerged within this shifting landscape. When exploited by unprivileged software, such weaknesses can reveal sensitive information or jeopardize entire computing platforms. This evolving threat landscape challenges decades of system security research, which traditionally centered on software vulnerabilities, and disrupts long-held assumptions about the inherent trustworthiness of hardware.

The workshop seeks to bring together leading researchers and experts from academia, industry, and government to foster knowledge exchange, generate innovative ideas, and engage in discussions on current challenges and future research directions. Key themes include security-by-design approaches for hardware, scalable assurance methodologies, and the integration of security considerations into electronic design automation.

Time and Venue

Date:
October 22-23, 2025

Location:
NIST, 100 Bureau Drive, Gaithersburg, Maryland 20899

Organizing Committee

Jay Rekhi and Yang Guo, National Institute of Standards and Technology (NIST)


Jeyavijayan Rajendran, Texas A&M University, USA


Gang Qu, University of Maryland, USA


Ahmad-Reza Sadeghi, TU Darmstadt, Germany

Steering Committee

Srini Devadas, MIT

 

Jeyavijayan Rajendran, Texas A&M

 

Ahmad-Reza Sadeghi, TU Darmstadt

 

Cliff Wang, NSF

 

Gang Qu, UMD

Confirmed Speakers and Panelists

Mary Bedner, NIST
Norman Chang, Ansys/Synopsys
Jason Fung, Intel
Blake Gray, Micron
Bernard McShea, DARPA
Jeremy Muldavin, Cadence
Warren Savage, ARLIS
Selcuk Uluagac, NSF
Jim Well, USAPAE
Greg Yeric, NSTC
Qiaoyan Yu, NSF
William Zortman, Sandia

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