The workshop seeks to bring together leading researchers and experts from academia, industry, and government to foster knowledge exchange, generate innovative ideas, and engage in discussions on current challenges and future research directions. Key themes include security-by-design approaches for hardware, scalable assurance methodologies, and the integration of security considerations into electronic design automation.
Time and Venue
Date:
NOVEMBER 8-12, 2026
Location:
SAN JOSE, CALIFORNIA, USA, San Jose Marriott
301 S Market St, San Jose, CA 95113
Organizing Committee
Jay Rekhi, National Institute of Standards and Technology (NIST)
Jeyavijayan Rajendran, Texas A&M University, USA
Ahmad-Reza Sadeghi, TU Darmstadt, Germany
Steering Committee
Srini Devadas, MIT
Jeyavijayan Rajendran, Texas A&M
Ahmad-Reza Sadeghi, TU Darmstadt
Cliff Wang, NSF
Gang Qu, UMD
Mary Bedner, NIST Norman Chang, Ansys/Synopsys Jason Fung, Intel Blake Gray, Micron Bernard McShea, DARPA Jeremy Muldavin, Cadence Warren Savage, ARLIS Selcuk Uluagac, NSF Jim Well, USAPAE Greg Yeric, NSTC Qiaoyan Yu, NSF William Zortman, Sandia